Prof. Dr. Erika Covi is an Assistant Professor at the Technical University of Munich (Germany), where she leads the Nanoelectronics Circuits and Systems (NCAS) Group. She received her Ph.D. in Microelectronics from the University of Pavia (Italy) in 2014. Following her doctoral studies, she was a researcher at the National Research Council (CNR) of Italy and Politecnico di Milano (Italy). She was later Senior Scientist at NaMLab gGmbH in Dresden, Germany, and Assistant Professor at the University of Groningen (the Netherlands).

Her research focuses on the intersection of emerging memory devices, circuit design, and brain-inspired computing, with an emphasis on design-technology co-optimization (DTCO). Her work explores how the intrinsic physical properties of novel memory technologies can be leveraged to develop energy-efficient computational systems by integrating emerging memory devices with CMOS circuits. She has been awarded with the ERC Starting Grant in 2021 and the ERC Proof of Concept in 2025.

Prof. Dr. Covi has co-authored approximately 50 publications in international journals and conferences, and she has served on the organizing committee of around 10 international conferences. She is a Senior Member of IEEE and serves on the Board of Governors of the IEEE Circuits and Systems Society.

Title of the presentation

Emerging Memory Integration for Energy-Efficient Edge Computing

The shift toward edge computing has enabled real-time data processing closer to the source of data collection, reducing latency and improving overall efficiency. Yet this shift imposes strict constraints on power consumption, physical footprint, and computational performance. These constraints cannot be met by conventional hardware approaches alone. At the same time, logic and memory technologies face increasing complexity as continued scaling necessitates consideration of multiple physical processes to sustain device, circuit, and system reliability. This complexity drives the need for Design-Technology-Co-Optimization (DTCO) and System-Technology-Co-Optimization (STCO) approaches, in which systems, circuits, and devices are co-designed to improve performance and address critical development challenges.

Non-volatile memory (NVM) devices show strong potential for enabling energy-efficient, massively parallel computing, owing to their CMOS-compatible operating voltages and analogue behaviour. Incorporating such emerging memory technologies at the back-end-of-line (BEOL) of CMOS circuits or within 3D array configurations opens significant opportunities for next-generation memory and computing systems. Realising this potential, however, requires addressing a set of critical obstacles: device variability, endurance limitations, fabrication compatibility, scalability, adequate compact models supporting circuit design, and system-level integration. These challenges are further compounded as SRAM and embedded DRAM scaling approach fundamental limits, increasing the relevance of Compute-In-Memory approaches and the emerging memory devices that underpin them.

This presentation highlights how DTCO and STCO provide the appropriate framework for navigating this complexity. By co-designing devices, circuits, and architectures in a holistic manner, and exploiting extended regimes of device behaviour, including low-power operation at low voltages, these approaches are of key importance for successfully integrating emerging memory technologies with CMOS circuits, enabling next-generation systems built on BEOL and 3D integration.