Elisa Vianello

Elisa is a Senior Scientist at CEA-Leti. Her primary research interests focus on the development of new technologies for highly energy-efficient, memory-centric computing. In 2022, she was awarded an ERC Consolidator Grant for her project “Heterogeneous integration of imprecise memory devices to enable learning from a very small volume of noisy data.” She has been a member of the VLSI Technical Program Committee (TPC) since 2023. Elisa received her Ph.D. in Electrical Engineering in 2010 through a joint program between the Università degli Studi di Udine (Italy) and the Grenoble Institute of Technology (INPG, France).

Abstract: In-Memory Computing for Trustworthy Edge AI: Bayesian Hardware and On-Chip Learning

Running AI on edge devices requires high efficiency under strict energy and latency constraints. In-memory and near-memory computing reduce data movement and improve efficiency. However, beyond efficiency, ensuring the trustworthiness of AI systems remains a critical concern. This talk introduces Bayesian electronics, where the intrinsic randomness of emerging nanodevices is used to encode probability distributions directly in hardware, enabling on-device uncertainty estimation. I will also present on-chip learning as a way to reduce reliance on cloud-based training, enabling local adaptation, improved privacy, and greater robustness. Recent hardware advances, including hybrid synaptic architectures that decouple inference from learning, will also be discussed.